1. Field of the Invention
The invention relates generally to microelectronic structures. More particularly, the invention relates to selective methods for forming microelectronic structures.
2. Description of the Related Art
As semiconductor device technology continues to advance, a need exists for semiconductor devices that provide enhanced performance within limited semiconductor substrate area. A class of semiconductor devices that has recently evolved to meet the foregoing performance and density needs is known as finFET devices.
FinFET devices are semiconductor devices that comprise a semiconductor fin located edgewise upon a substrate. A pair of gate dielectric layers is typically located one each upon both major vertical surfaces, and optionally also contiguously upon a top surface, of the semiconductor fin. An inverted U shaped gate electrode often straddles a central section of the semiconductor fin and covers the gate dielectric layers. In other instances, a portion of a gate electrode is not located atop the semiconductor fin, and thus a pair of gate electrodes is restricted to the sidewalls of the semiconductor fin. End portions of the semiconductor fin uncovered by the gate electrode are typically subject to ion implantation while using the gate electrode or other masking layer as a mask, to thus provide source/drain regions within the semiconductor fin that are separated by a channel region located beneath or covered by the gate electrode(s) within the semiconductor fin.
FinFET devices provide several advantages in comparison with conventional planar field effect transistor devices. In particular, since finFET devices are vertical channel devices, they may be scaled effectively in the vertical direction, while not using any additional semiconductor substrate area. Thus, finFET devices offer an opportunity for enhanced semiconductor device performance absent an increase in aerial dimensions.
FinFET devices clearly provide a novel approach for increasing semiconductor device performance. However, finFET devices are not entirely without difficulty. FinFET fabrication generally involves forming a gate electrode having a considerable thickness upon a semiconductor fin that might also be readily scaled to a considerable height. The topography induced by the crossing of such a fin structure with such a gate structure may, under certain circumstances, provide fabrication difficulties.
A need thus exists for providing finFET structures, and methods for fabrication thereof, that are readily manufacturable.